There has been drastic improvement in LSI chips constituting computers and other information processing units, and output signal speed produced by each LSI chip is still getting faster. The LSI chips include, for example, SRAM, SDRAM, microprocessor, in which remarkable performance enhancement have been achieved. Such LSI chips are mounted on a printed circuit board, and high frequency signals are transmitted between these chips through signal transmission paths provided on the printed circuit board. Also, in an LSI such as an ASIC, high frequency signals are transmitted between high-speed circuit blocks.
The faster the signal transmission between circuit blocks or chips, or in an electronic device case is, the greater the signal attenuation in the transmission paths becomes. In such a signal that alternately repeats the H level and the L level, time margin for the reception signal to swing up to full amplitude becomes less, so that the amplitude of the reception signal is decreased. To cope with such a case, it is required to obtain a receiver circuit having high sensitivity, operating at high speed, and enabling accurate reception, even though high-frequency components in the reception signal is attenuated.
As a sample-and-hold circuit enabling extraction of reception signals stably at high speed, there has been proposed an analog comparator which converts a received analog signal to a digital signal by switching a current source of a bipolar transistor on and off by a sampling clock. (For example, [Official gazette of the Japanese Unexamined Patent Publication No. Sho-54-103651])
Also, there has been proposed a sample-and-hold circuit consisting of CMOS circuits, which alternately samples input signals through transfer gates, alternately amplifies in two differential amplifier circuits, and latches the amplified result. (For example, [Official gazette of the Japanese Unexamined Patent Publication No. 2002-368592])
Further, FIG. 1 shows a diagram illustrating an example of the conventional receiver circuit capable of dealing with high-speed reception signals. In order to receive high-frequency reception signals, reception data are demultiplexed in the vicinity of input data line of the receiver circuit to the possible extent, and in order to convert the reception signal to a low-frequency reception signal. The receiver circuit shown in FIG. 1 samples differential reception signals RXIP, RXIN by CMOS transfer gates P1, N2 and P3, N4, and a differential amplifier circuit amplifies the reception signals having been sampled at the nodes nd1, nd2. In the figure, a P-channel MOS transistor is denoted by a reference symbol P, while an N-channel MOS transistor is denoted by a reference symbol N. Also, a node is denoted by nd.
Referring to FIG. 1, the differential amplifier circuit includes: transistors N5, N6, of which sources are commonly connected; a switch transistor N7, which activates the amplifier circuit when a clock CLK lies in the H level; precharge transistors P9, P10, which precharge differential amplification output nodes ndn, ndp to a power supply voltage Vdd level while the clock CLK lies in the L level; and transistors P8, P11, P12, N13 and N14 constituting a regenerative latch circuit. The differential amplification output nodes ndn, ndp are supplied to an output latch circuit which consists of NAND gates 10, 12 having intersected connections between each output and input.
An operation waveform diagram of this receiver circuit is illustrated also in the figure. During the period of the clock CLK lying in the L level (or, the period of the reverse phase clock /CLK lying in the H level), the output nodes ndn, ndp of the differential amplifier are precharged to the power supply voltage Vdd level. During this period, the transfer gates P1, N2 and P3, N4 are controlled to be a conducting condition, and the differential input signals transmitted through transmission paths in the printed circuit board or the system circuit are sampled to parasitic capacitor of the input nodes nd1, nd2. When the clock CLK becomes H level, the transfer gates are controlled to be a non-conducting condition, and the differential amplifier circuit becomes to be separated from the input data line. Also, the transistors P9, P10 in the precharge circuit and the transistor P8 become non-conducting, and the switch transistor N7 becomes conducting. Thus the differential amplifier circuit detects the level of the input nodes nd1, nd2.
When the input node nd1 is in H level and the node nd2 is in L level, the current through the transistor N5 becomes greater than the current through the transistor N6, and the voltage level of the output node ndp drops faster than the voltage level of the output node ndn. In response to the voltage drop of the node ndp, the transistor N14 becomes non-conducting, and the transistor P12 becomes conducting. The voltage of the node ndn then rises again to the power supply voltage Vdd level, and thus the large voltage difference is produced between the output nodes ndp and ndn. Namely, by the regenerative latch circuit, the L level is generated in the output node ndp, and the H level is generated in the output node ndn. The H level and the L level produced above are respectively latched by the NAND gates 10, 12.